LOW VOLTAGE DIFFERENTIAL SIGNALING - LVDS

Recent growth in high-end processors, multi-media, virtual reality and networking has demanded more bandwidth than ever before. But the point-to-point physical layer interfaces have not been able to deal with moving information at the data rates required. Some of today’s biggest challenges that remain to be solved include: the ability to transfer data fast, lower power systems than currently available, and economical solutions to overcome the physical layer bottleneck.

Data Transmission standards like RS-422, RS-485, SCSI and others all have their own limitations most notably in transferring raw data across a media. Not anymore. Low Voltage Differential Signaling (LVDS) is a high speed (>155.5 Mbps), low power general purpose interface standard that solves the bottleneck problems while servicing a wide range of application areas.

This application note explains the key advantages and benefits of LVDS technology. Throughout this application note the DS90C031 (LVDS 5V Quad CMOS Differential Line Driver) and the DS90C032 (LVDS 5V Quad CMOS Differential Line Receiver) will be used to illustrate the key points. Over 50 LVDS devices are offered currently (1998) from National, please refer to the LVDS device datasheets for complete specifications.

Low-voltage differential signaling, or LVDS, is an electrical signaling system that can run at very high speeds over inexpensive twisted-pair copper cables. It was introduced in 1994, and has since become very popular in computers, where it forms part of very high-speed networks and computer buses.       

Low-voltage differential signaling (LVDS) is a signaling method used for high-speed transmission of binary data over copper. It is well recognized that the benefits of balanced data transmission begin to outweigh the costs over single-ended techniques when signal transition times approach 10 ns. This represents signaling rates of about 30Mbps or clock rates of 60MHz (in single-edge clocking systems) and above. LVDS, as documented in TIA/EIA-644, can have signal transition time as short as 260ps turning a printed circuit board trace into a transmission line in a few centimeters. Care must be taken when designing with LVDS circuits, such as the SN65LVDS31 quadruple line driver and SN65LVDS32 quadruple line receiver. This document provides some guidelines for the basic application of LVDS.

What is Differential Signaling?

Differential signaling is a method of transmitting information electrically by means of two complementary signals sent on two separate wires. The technique can be used for both analog signaling, as in some audio systems, and digital signaling, as in RS-422, RS-485, Ethernet (twisted-pair only), PCI Express and USB. The opposite technique, which is more common but lacks some of the benefits of differential signaling, is called single-ended signaling.

There are plenty of choices when selecting a high-speed differential signaling technology. Differential technologies generally share certain characteristics but vary widely in performance, power consumption, and target applications. Table 1-1 lists various attributes of the most common differential signaling technologies.

         

Industry standards bodies define LVDS and M-LVDS technologies in specifications ANSI/TIA/EIA-644A and ANSI/TIA/EIA-899, respectively. Some vendor datasheets claim LVDS I/Os (or pseudo-LVDS) but in fact may not meet the required common mode or some other important parameter. Therefore, compliance to the LVDS specification TIA/EIA-644A is an important consideration.Current-Mode Logic (CML) and Low-Voltage Positive-Emitter-Coupled Logic (LVPECL) are widely used terms throughout the industry, although neither technology conforms to any standard controlled by an official standards organization. Implementations and device specifications will therefore often vary between vendors. AC coupling is used extensively which helps resolve threshold differences that might otherwise cause compatibility issues. Note that all of the technologies listed are differential and thus share the advantages common to differential signaling such as excellent noise immunity and low device-generated switching noise.

        

	Industry Standard	Maximum Data Rate	Output Swing(Vod)	Power Consumption
LVDS	TIA/EIA-644	3.125Gbps	± 350 mV	Low
LVPECL	N/A	10+Gbps	± 800 mV	Medium to High
CML	N/A	10+Gbps	± 800 mV	Medium
M-LVDS	TIA/EIA-899	250 Mbps	± 550 mV	Low
B-LVDS	N/A	800 Mbps	± 550 mV	Low

                        

                           Table 1-1. Industry Standards for Various LVDS Technologies

A typical LVDS driver – receiver pair is shown in Figure 1. A (nominal) 3.5mA current source is located in the driver. Since the input impedance of the receiver is high, the entire current effectively flows through the 100Ω termination resulting in a (nominal) 350 mV voltage across the receiver inputs. The receiver threshold is guaranteed to be 100 mV or less, and this sensitivity is maintained over a wide common mode from 0V to 2.4V. This combination provides excellent noise margins and tolerance to common-mode shifts between the driver and receiver. Changing the current direction results in the same amplitude but opposite polarity at the receiver. Logic ones and zeros are generated in this manner. CML and LVPECL have a similar architecture but with different strength current sources and termination schemes.

From this simple diagram in Figure 2, the advantages common to all differential signaling technologies can be seen. First,  note that the current source is always on and routed in different directions to drive logic ones and zeros. This always-on characteristic eliminates the switching-noise spikes and EMI resulting from turning high-current transistors on and off (as required in single-ended technologies). Secondly, the two lines of the differential pair are adjacent to each other providing a considerable amount of noise immunity.

Noise from crosstalk or EMI that is absorbed in one of the pair will also appear in the adjacent line. Since the receiver responds to the difference between the two channels, “common-mode” noise that appears on both lines of the pair will cancel at the receiver. Also, as the two adjacent lines carry equal current, but in opposite directions, EMI generation is minimized.

Low-Voltage Differential Signaling

Definition and Overview:

Low-voltage differential signaling (LVDS) uses high-speed analog circuit techniques to provide multi gigabit data transfers on copper interconnects and is a generic interface standard for high-speed data transmission.

The American National Standards Institute (ANSI)/Telecommunications Industry Association (TIA)/Electronic Industries Alliance (EIA)–644-1995 standard specifies the physical layer as an electronic interface. This standard defines driver and receiver electrical characteristics only. It does not define protocol, interconnect, or connector details because these details are application-specific.

The LVDS Standard’s Working Group chose to define only the electrical characteristics to ensure that LVDS becomes a multipurpose interface standard. Therefore, each application that uses LVDS should also reference the appropriate protocol and interconnect standard.

The 350 mV typical signal swing of LVDS consumes only a small amount of power and therefore LVDS is a very efficient technology, delivering performance at data rates up to 3.125Gbps. The simple termination, low power, and low noise generation generally make LVDS the technology of choice for data rates from tens of Mbps up to 3Gbps and beyond.

For higher data rates, technologies such as CML or LVPECL are required. As shown graphically in Figure 3 and 4, CML and LVPECL are capable of very high data rates in excess of 10Gbps. Achieving these very high data rates requires extremely fast, sharp-edge rates and typically a signal swing of approximately 800 mV. For these reasons, CML and LVPECL generally require more power than LVDS.

Standard Overview:

There are two industry standards that define LVDS. The more common of the two is the generic electrical layer standard defined by the TIA. This standard is know as ANSI/TIA/EIA-644. The other application specific standard is an IEEE (Institute for Electrical and Electronics Engineering) standard titled Scalable Coherent Interface (SCI).

ANSI/TIA/EIA-644

This standard was developed under the Data Transmission Interface committee TR30.2. This standard defines driver output and receiver input characteristics. Functional specifications and/or Protocols are not within the scope of the TlA standard. It notes a recommended maximum data rate of 655 Mbps and a theoretical maximum of 1.923 Gbps based on a loss-less media; however, maximum data rate is application (desired signal quality), and device specific (transition time). It is feasible that LVDS based interface will operate in the 500 Mbps to 1.5Gbps range in the near

future. Minimum media specifications are also defined within the standard. It also discusses failsafe operation of the receiver under fault conditions and other configurations issues such as multi-receiver operation. National Semiconductor held the editor position for this standard.

IEEE 1596.3 SCI-LVDS

SCI originally referenced a differential ECL interface within the SCI (Scalable Coherent Interface) 1596-1992 IEEE standard. But, this only addressed the high data rates required and did not address the low power concerns. Thus, SCI-LVDS was defined as a subset of SCI, and is specified in IEEE 1596.3 standard. SCI-LVDS specifies signaling levels (electrical specifications) for the high speed/low power physical layer interface. It also defines the encoding for packet switching used in SCI data transfers.

Packets are constructed from 2-byte (doublet) symbols. This is the fundamental 16-bit symbol size. No media is specified and the data rate can be in the order of 500 MT/s based on serial or parallel transmission of 1, 4, 8, 16, 32, 64bits.

SCl-LVDS also supports Ram Link for super low power data transmission in a restricted environment. The IEEE 1596.3 standard was approved in March 1994. National Semiconductor held the Chairperson position for this standard. SCI-LVDS is similar to the TIA version but differs in some electrical requirements and load conditions. Both standards feature similar driver output levels, receiver thresholds and data rates. The TIA version is the more generic of the two standards and is intended for multiple applications.

The Trend to LVDS:

Low-Voltage Differential Signaling (LVDS) is a new technology addressing the needs of today’s high performance data transmission applications. The LVDS standard is becoming the most popular differential data transmission standard in the industry. This is driven by two simple features: “Gigabits @ milliwatts!” Consumers are demanding more realistic visual information in the office and in the home. This drives the need to move video, 3D graphics and photo-realistic image data from cameras to PCs and printers through LAN, phone, and satellite systems to home set-top boxes and digital VCRs. Solutions exist today to move this high-speed digital data both very short and very long distances, on printed circuit boards (PCB) and across fiber or satellite networks. Moving this data from board-to-board or box-to-box however, requires an extremely high-performance solution that consumes a minimum of power, generates little noise, (must meet increasingly stringent FCC/CISPR EMI requirements) is relatively immune to noise, and is cost-effective.

National Semiconductor first introduced LVDS as a standard in 1994. National recognized that the demand for bandwidth was increasing at an exponential rate while users also desired low power dissipation. This exceeded the speed capabilities of RS-422 and RS-485 differential transmission standards. While Emitter Coupled Logic (ECL or PECL) was available at the time, it is incompatible with standard logic levels, uses negative power rails, and leads to high chip-power dissipation. These factors limited its wide spread acceptance.

LVDS is differential, using two signal lines to convey information. While sounding like a penalty, this is actually a benefit. The cost is two traces (or conductors) to convey a signal, but the gain is noise tolerance in the form of common-mode rejection.

Operation of LVDS:

LVDS is a low swing, differential signaling technology, which allows single channel data transmission at hundreds or even thousands of Megabits per second (Mbps). Its low swing and current-mode driver outputs create low noise and provide very low power consumption across a wide range of frequencies.

As shown in Figure 1, LVDS outputs consist of a current source (nominal 3.5mA) that drives the differential pair lines. The basic receiver has a high DC input impedance, so the majority of driver current flows across the 100W termination resistor generating about 350 mV across the receiver inputs. When the driver switches, it changes the direction of current flow across the resistor, thereby creating a valid “one” or “zero” logic state.

DATA TRANSMISSION BASICS

Data transmission, as the name suggests, is a means of moving data from one location to another. Choosing the best transmission standard to accomplish this requires evaluation of many system parameters. The first two considerations encountered are How fast? and How far? How fast? refers to the signaling rate or number of bits transmitted per second. How far? is concerned with the physical distance between the transmitter and receiver of the data. Consideration of these two primary system parameters usually results in a significant narrowing of the possible solutions. Figure 5 shows the speed and distance coverage of some familiar data transmission choices.

LVDS Features

LVDS technology uses differential data transmission. The differential scheme has a tremendous advantage over single-ended schemes as it is less susceptible to common mode noise. Noise coupled onto the interconnect is seen as common mode modulations by the receivers and is rejected. The receivers respond only to differential voltages. LVDS technology is not dependent on a specific power supply, such as +5V. This means there is an easy migration path to lower supply voltages such as +3.3V, +2.5V or even lower while still maintaining the same signaling levels and performance.

Technologies like ECL or PECL are more dependent on the supply voltage. This feature is highly desirable in any application that foresees moving to lower supply voltages without substantial redesign or worrying about mixed voltage operation (+5V/+3.3V) on system boards.

To achieve high data rate, low power and to reduce EMl effects, signaling levels have to be reduced. The DS90C031/DS90C032 chipset’s limitation on data rate is mainly dependent on the technology driving the LVDS drivers. The aggregate bandwidth that LVDS technology can drive is in the Gbps range with a loss-less media. Data rates in the 500-1,000 Mbps are possible and this limitation is primarily dependent on the media being driven.

SIGNALING LEVELS:

As the name implies, LVDS features a low voltage swing compared to other industry data transmission standards. The signaling levels are illustrated in Figure 6, and a comparison to PECL levels is also shown as reference.

Because of the low swing advantage, LVDS achieves a high aggregate bandwidth in point-to-point applications. National has recently introduced a new family of parts called Bus LVDS. This family extends LVDS from point-to-point applications to multi-point applications is fully discussed in other National application notes. Bus LVDS features similar voltage swings, but provides increased drive current to handle double terminations required in multi-point applications. It is impossible to achieve high data rates and provide low power without utilizing low voltage swings. LVDS signaling levels are smaller (50%) than PECL levels as shown in Figure1. EMI effects are also reduced as the signaling swings are much smaller than traditional CMOS, TTL or even PECL. This is due to the current mode drivers, the soft transitions, the low switching currents and the use of true differential data transmission.

LVDS TERMINATION:

LVDS uses a constant current mode driver to obtain its many features. The value of the current source for the DS90C031 is a maximum of 4.5mA. The transmission media must be terminated to its characteristic impedance to prevent reflections. Typically this is between 100W–120W and is matched to the actual cable. A termination resistor is required to generate the Differential Output Voltage (VOD) across the resistive termination load at the receiver input (see Figure 8 a)

Data transmission from the driver to receiver without the termination is not recommended. The simplicity of the LVDS termination scheme makes it easy to implement in most applications. It is recommended to have a single 100W termination between the driver outputs, and the use of surface mount components is also recommended to reduce the effects of parasitic. The single resistor approach is the most common LVDS termination method because of its simplicity. Proper termination not only avoids reflection problems, but also reduces unwanted electromagnetic emissions.

The user may also use a cable damping resistor with a capacitor to ground as shown in Figure 8b. This method provides additional common mode termination. Due to the additional complexity, this approach is not too common. ECL and PECL require more complex terminations than the “one” resistor solution for LVDS. PECL drivers typically require 220W pull down resistors from each driver output to ground along with the 100W across the driver outputs as shown in Figure 8c.  This termination method requires additional PCB space and increases system cost compared to the single resistor LVDS termination.

COMMON MODE RANGE:

An LVDS receiver can tolerate a minimum of ±1V ground shift between the driver’s ground and the receiver’s ground. Note that LVDS has a typical driver offset voltage of +1.2V,and the summation of ground shifting, driver offset voltage and any longitudinally coupled noise is the common mode voltage seen on the receiver input pins with respect to the receiver ground. The common mode range of the receiver is +0.2V to +2.2V, and the recommended receiver input voltage range is from ground to +2.4V.

For example, if a driver has a VOH of 1.4V and a VOL of 1.0V (with respect to the driver ground), and a +1V ground shift is present (driver ground +1V higher than receiver ground), this will become +2.4V (1.4+1.0) as VIH and +2.0V (1.0+1.0) as VIL on the receiver inputs referenced to the receiver ground (+2.2V VCM). Similarly, with a −1V ground shift and the same driver levels results as 0.4V (1.4−1.0) VIH and 0.0V (1.0−1.0) VIL on the receiver inputs (+0.2V VCM). This is shown graphically in Figure 7.

FAIL SAFE FEATURE:

Failsafe is a receiver feature that guarantees the output to be in a known logic state (HIGH) under certain fault conditions. This occurs when the inputs of the receiver are either open, shorted or terminated.

In some applications, not all receivers of the Quad DS90C032 may be used. In this case, the unused receiver inputs should be left open. If the receiver does not support failsafe and the inputs are left open (See Figure 9), any external noise above the receiver threshold can trigger the output and cause an error on the communication line. Since the DS90C032 supports open input failsafe, the receiver output will provide an output High for this case.

Another fault condition can occur if the inputs get accidentally shorted (See Figure 4 ). Under the above condition, the receiver output will also be at logic High and not in an unknown state. Another case could occur if the driver is either powered off, in TRI-STATE® or even removed from the line while the receiver stays powered on with inputs terminated by the 100W termination resistor.

The receiver output will provide a logic high under all the above mentioned conditions. Failsafe support is receiver device dependent, please refer to the specific LVDS receiver datasheets to determine which level of failsafe support is provided. Remember that the receiver function is to amplify very small (mV), short duration (ps-ns) pulses to rail-to-rail CMOS levels. System design should ensure that noise picked up on the interconnect is seen as common and not differential. This can be accomplished by using balanced cables, shielding from noise sources and closely-coupled differential traces on PCBs.

POINT-TO-POINT CONFIGURATIONS:

For interfaces where the transition time of the driver is substantially shorter than the time delay of the media, the interconnection must be considered a distributed load, not a lumped load. The distributed elements of a transmission line (media) can greatly affect signal quality.

More explicitly, transmission line theory dictates that if the transition (rise or fall) time of the driver is less than four times the line delay, the media must be treated as a distributed load, not a lumped load, and careful attention must be paid to any impedance discontinuities and stubs. For a given driver, if tr < 4 td (where tr = driver rise time, td = delay of the line) then the line should be considered as a lossy line. This is usually true if the tr of drivers are in the sub nanosecond range. A quick calculation will clarify this rule of thumb.

For example, the DS90C031 driver has a typical tr of 350 ps, and a microstrip built with FR-4 material has a td of 147 ps for one inch of PC trace. This calculates that, an inch of FR-4 microstrip will act as a transmission line (350 < 4*147) when driven by the DS90C031 driver. Figure 10 includes a stub between the termination resistor and the receiver input. This length must not be longer than one inch in length and should be kept as short as possible. Stub lengths of 1 inch or greater will cause the propagating signal to bounce off the high impedance end of the stubs and degrade the signal. Multiple reflections can travel up and down the line causing ringing, overshoot and undershoot which reduces the noise margin too. The fast tr of the DS90C031 allows the driver to achieve a higher bandwidth, but transmission line characteristics can easily crop up on a system board if not handled properly at these edge rates.

 To make the device work to its fullest capability, the LVDS DS90C031 and the DS90C032 should be operated in a point-to-point configuration with minimum discontinuities on the transmission line. This ensures no stub problems on the line. The media must be terminated by a 100W line-to-line termination at the far end.

 A 100W termination resistor terminates the two differential line in its characteristic impedance and also provides the differential voltage (VOD) for the current mode driver. Under the above conditions, the driver can drive a twp (twisted pair) wire over 10m at speeds in excess of 155.5 Mbps (77.7 MHz). Note that other LVDS devices offered by National support higher data rate operation. The FAST LVDS family of parts support 400Mbps operation, and the Channel Link family of LVDS parts operate even faster on the LVDS lines.