In 1984 Drs. Arthur Pohm and Jim Daughton, both employed at that time by Honeywell, conceived of a new class of magnetoresistance memory devices  which offered promise for high density, random access, nonvolatile memory. In 1989 Dr. Daughton left Honeywell to form Nonvolatile Electronics, Inc. having entered into a license agreement allowing him to sublicense Honeywell MRAM technology for commercial applications. Dr. Pohm, Dr. Daughton, and others at NVE continued to improve basic MRAM technology, and innovated new techniques which take advantage of revolutionary advances in magnetoresistive devices, namely giant magnetoresistance and spin dependent tunneling.

  Today there is a tremendous potential for MRAM as a nonvolatile, solid state memory to replace flash memory and EEPROM where fast writing or high write endurance is required, and in the longer term as a general purpose read/write random access memory. NVE has a substantial patent portfolio containing 10 MRAM patents, and is willing to license these, along with 12 Honeywell MRAM patents, to companies interested in manufacturing MRAM. In addition, NVE is considering internal production of certain niche MRAM products over the next several years.


    MRAM is a nonvolatile random access memory which uses magnetic storage and  magnetoresistance (MR) to read the stored data. Magnetoresistive material is a resistor made of common ferromagnetic material which will change in resistance in the presence of a magnetic field. The magnetoresistive property gives a small but sufficient signal to distinguish between a “1” and “0”. MRAM results from combining MR storage elements with standard semiconductor fabrication processes. The magnetic devices are integrated with support circuits on a single silicon chip to duplicate the function of a static semiconductor RAM chip. The magnetic storage elements are formed from a layer of  permalloy  thin  film where the
intersection of the permalloy (sense line) and metal layer (word line) form a memory bit.

   The general attributes of MRAM are:
• Nonvolatility
• Infinite write cycling without wearout
• Fast write (few nanoseconds for advanced modes)
• Low write energy
• Nondestructive read.

   When combined with the high density of advanced GMR cells, these attributes lead to the “perfect memory” with speed, density and limited cycling of SRAM and DRAM and the nonvolatility of EEPROM, flash and other nonvolatile memories. In random access magnetoresistive memories (MRAM), storing data is accomplished by applying magnetic fields and thereby causing a magnetic material in a cell to be magnetized into either of two possible memory states. Recalling data is accomplished by sensing resistance changes in the cell when magnetic fields are applied. The magnetic fields are created by passing currents through strip lines (word lines) external to the magnetic structure, or through the magnetic structures themselves (sense lines). MRAM cells are narrow stripes etched into a multi-layer thin film stack of permalloy–copper–permalloy. Data is stored by magnetizing the stripe.


   The    development of   MRAM    has  been based  on a number of significant ideas over the past 20 years, starting with Anisotropic Magnetoresistance (AMR) materials and then using higher sensitivity Giant Magnetoresistance (GMR) and Spin Dependent Tunneling (SDT) materials. A brief background on precursors to  magnetoresistive random access by a description of an early MRAM, and then descriptions of cell configurations with improved signal  levels including MRAM cells with GMR materials and cells using SDT  structures.

  The two  methods used for data storage in MRAM cells are :

1.     2-D Magnetic Write Selection.
2.     1-D Magnetic Write Selection .

2-D Write Selection Scheme
  Early magnetic random access memory (as opposed to serial memories like tape and disk) used the natural hysteresis of magnetic materials to store data (‘1” or “0”) by using two or more current carrying wires or straps. Magnetic elements were arrayed so that only ones which were to be written received a combination of magnetic fields above a write threshold, while the other elements in the array did not change storage state. A simple version of 2-D write selection scheme is shown in the figure given below. Most of today’s MRAM concepts still use this write selection technique.

·        Ix, Iy Alone Doesn’t Switch Cell
·        Ix,Iy together switch the  Cell

  Selected cells receive both Ix and Iy currents, and are switched  into    the desired   memory states. The currents  must be selected so that Iy or Ix separately do not disturb the memory state of stored

data.   Bits on the same x line or y line that are not  being written are subjected to "half-select" currents which tend to disturb the  data. If very  large currents are used to insure the writing of worst case cells, then the half-select currents are    also large and   tend to
disturb the  most  disturb-sensitive cells. The  half-selected memory states are also not nearly as stable as stored bits, and they provide  the majority of

projected cell failures in time In addition to  half-select currents, these cells must withstand stray fields from  neighboring cells and fields from leakage currents and stray environmental fields. Thus, the requirements for uniformity and design margins present challenges in manufacturing the 2D magnetic arrays.

  Most magnetoresistive  memory    schemes also use a 2D  selection scheme  for reading data. The original  MRAM  concept and the pseudo-spin valve (PSV)  concept both use magnetic 2D selection schemes for reading, which introduce further disturb conditions.

1-D Magnetic Selection Scheme
     In  this new scheme, a select  transistor  per memory  cell  is used for writing  and  a  much smaller    current is  used    for reading  than for writing. This should  result in substantially wider process margins, but probably  at  the  sacrifice of density  due  to  the size of   the required transistor in  the  cell. This  “1D magnetic select" scheme is potentially ideal for small, high performance nonvolatile RAM .

       The   transistor   provides  the  selection  of  the memory cell and not the

   magnetic switching properties of  the  cell. A very large current can be used  to write and  a  small  current can  be used to read the cell, thus providing  potentially  very  large margins. Of course it  is important to use as small a current as will reliably write the cell so as to reduce the size of the transistor needed for selection. There are still 2D arrays of cells, but the transistors take up the burden of selection rather than placing severe constraints on the magnetic switching properties of the cell. This is why this is called a "1D magnetic selection". The scheme is quite similar to that used for DRAM where a transistor is used to write and detect charge on a capacitor.


The two methods that are used for data retrieval from MRAM cells are :
1.     Inductive  readout  scheme.
            The early memories (mostly magnetic core memories) used inductive
signals for determining the storage state (“1” or “0”). A magnetic field     (current)   was used to “interrogate” the memory element, and the polarity of

induce    voltages in a sensing circuit depended on whether a “1” or “0” was stored.

2.     Magnetoresistive readout scheme.
             The first to propose a magneto-resistive readout scheme was Jack Raffel . Magnetoresistance ratio is the ratio of change in electrical  resistance
to minimum resistance of a  magnetic material when it is subjected to an electric field .  His scheme stored data in a magnetic body, which in turn produced a stray   magnetic field that could be detected by a separate magnetoresistive sensing    element. The concept was not high density because it was difficult to get a    sufficiently large external stray field from a small magnetic storage cell. This scheme is used in most of today’s MRAM cells.

    There were difficulties in getting the cell to write consistently, and the difference in resistance between a “1” and “0” .was only about 0.1% of the inherent cell resistance, an impractically low signal.

   The first published proposal for fabricating magnetic memory cells on a silicon support chip used inductive read-out rather than magnetoresistive readout . This was (and still is) an important concept for MRAM because interconnections between an array of magnetic cells and the required

circuitry to make a memory are probably too complex for separate memory and support circuitry.
   In the mid 1980’s an MRAM concept was developed at Honeywell which has some common features with most modern versions.

1. Writing using magnetic hysteresis.
2. Reading using magnetoresistance of the same body where data is stored.
3. Memory cells integrated on an integrated circuit chip.

    Figure 3 illustrates the working of an AMR cell. The cell consisted of two ferromagnetic films sandwiching a poor conductor (TaN), with the composite film etched into stripes as shown.

    A current through the stripe magnetized the NiFe clockwise or counterclockwise when aided by a current (field) from an orthogonal stripline. Current in either strip by itself would not change the storage state. Thus, a single memory cell could be selectively written in a 2D array.

        Reading of this cell depended on the differential resistance of the cell
when a sense current was passed through it. Because the sense current creates a magnetic field which opposes the magnetization in one storage state, but is in the same direction in the other state, the angle of rotation was different for a “1” or “0”. The magnetic material used was a cobalt-permalloy  alloy with a normal anisotropic magnetoresistance (AMR) ratio of about 2%. Despite    improvements in reading methods , the maximum differential resistance of the cell between a “1” and a “0” when it was read was about ¼ of the 2% magnetoresistance, or about 0.5%. In real arrays with practical sense currents, this gave differential sense signals of 0.5 to 1.0 mV. These sense signals allowed 16K bit integrated MRAM chips to operate with a read access time of about 250 ns . Write times for the MRAM was 100 ns, and could have been faster if needed.


   The Giant Magnetoresistance was discovered in 1988 independently by Baibich et al. in Paris and Binasch et Jülich. It is the phenomenon
where the resistance of certain materials drops dramatically as a magnetic field is applied. It is described as Giant since it is a much larger effect than had ever been previously seen in metals.

   The effect is most usually seen in magnetic multilayered structures, where two magnetic layers are closely separated by a thin spacer layer a few nm thick. It is analogous to a polarization experiment, where aligned polarizers allow light to pass through, but crossed polarizers do not. The first magnetic layer allows electrons in only one spin state to pass through easily - if the second magnetic layer is aligned then that spin channel can easily pass through the structure, and the resistance is low. If the second magnetic layer is misaligned then neither spin channel can get through the structure easily and the electrical resistance is high.

  The GMR effectively measures the difference in angle between the two magnetisations in the magnetic layers. Small angles (parallel alignment) gives a low resistance, large angles (anti-parallel alignment) gives a higher resistance. It is easy to produce the state where the two magnetic layers are parallel - simply apply a field large enough to magnetically saturate both layers. But how do we achieve an anti-parallel state? There are three basic ideas used here:

1.     Antiferromagnetic coupling:
When the spacer layer is extremely thin the sense of the coupling between the two layers oscillates. In other words, for certain specific values of the spacer thicknesses the magnetisations of neighbouring layers will naturally wish to lie in opposite directions. By applying a large enough magnetic field we can force the magnetisations of the layers to all line up along the field direction. In this way it is possible to get the two different resistance states.

2.Different Coercivities:

If we use two different materials with different switching fields then as we apply the reverse field one layer will switch before the other

 we then have the desired anti-parallel alignment. In practice the contrast between the layers has to be good, and most materials do not switch sharply enough to get the full benefit from this technique. We have grown {Co/Cu/Fe/Cu}xN multilayers by MBE which show this sharp switching behaviour. These types of structures are sometimes called 'pseudo' spin valves.

      3.Exchange biasing & spin-valves:

It is possible to exchange couple one of a pair of magnetic layers to another back layer of antiferromagnetic material. In the diagram below an FeMn layer is used to 'pin' the Co layer magnetisation in a 

certain direction. This layer is used as a reference layer. The NiFe layer, which is  magnetically soft, can now be aligned parallel or anti-parallel by very tiny fields. There is a thick enough Cu spacer between these two to stop there from being any magnetic coupling between the layers. The Ta layers are a buffer (to give a good surface to grow on) and a cap (to stop the sample from being oxidised in air). The whole sample is deposited on a piece of Si wafer, which is in fact many thousands of times thicker than the whole multilayer structure.

GMR by Analogy and its Origin in Spin-Dependent Scattering

  Giant magnetoresistance   may be most easily understood through a simple optical analogy. If a beam of unpolarized light is directed through a pair of polarizers, the total  transmitted intensity can be modulated by rotating  the polarizers with respect to  each other. The first polarizer scatters all but one polarization  of  light , and the second  polarizer  either  transmits that same
polarization (0°)or blocks it (90 ° ).

  For GMR, electrons take the place of photons, thin ferromagnetic materials act as electronic polarizers, and the polarization is in terms of spin rather than electric field.

    Giant magne-toresistance takes place only in a thin-film super-lattice stack of at least three films: two ferromagnetic layers, most typically NiFe or Co, separated by a noble metal spacer layer, usually Cu. These films are ultrathin, on the order of ten atomic layers each.

  The polarization axis is provided by the magnetization of the ferromagnet through spin-dependent scattering.

   Conduction electrons with spin parallel to the layer magnetization are scattered weakly close to the layer, carrying current more effectively and leading to low resistance, and those with spin anti-parallel to the magnetization are scattered strongly, leading to high resistance. For parallel alignment of the two layer magnetizations, the electrons transmitted strongly through one ferromagnetic layer are transmitted strongly through the other, leading to a lowered overall resistance. For anti-parallel magnetization, strong scattering will take place in either one of the layers for both spins. By changing the relative magnetization of alternate layers from parallel to anti-parallel, a very large room-temperature change in the resistance may be produced. The effect is largest for current passed perpendicular to the film planes.


    AMR materials showed a magnetoresistance ratio  of only 2%.The memory arrays in these memories sense relatively small signals (1mv) , leading to  a read  access time of about 250 ns. GMR materials showed a magnetoresistance ratio of about 6% .Since the read access times tends to

improve as the square of the signal, normal scaling would indicate that the improvement of a factor of 3 in magnetoresistance would lead to a 9 times improvement in read access time. Read access times of under 50 ns were achieved for MRAM with GMR materials.

    A primary factor determining read access time in MRAM is the signal-to-noise ratio. New GMR cells which can store data at very high densities, and yet give greatly improved  signal levels have been developed like the Pseudo-Spin Valve  (PSV) cell. It is suitable for 0.5 micron width down to at least  0.1 micron width per MRAM cell (or memory bit). These cells are efficient and use  nearly  all   the    available  intrinsic    magneto-resistive signal of the cell, and are therefore much faster and denser than the original AMR cell concept.

   In AMR materials the  change in  resistance depends on the relative direction between film magnetization and in-plane current direction whereas in case of GMR materials , resistance depends on the relative orientation between the neighbouring magnetic layers. It is a maximum when the directions are anti-parallel and a minimum when they are parallel.


   Even with GMR materials this cell had serious limitations. The competition – semiconductor  memory –  was   still  faster  because  of  the  low  MRAM sense signal. Worse, there was a limit to the reduction of cell size because the cell would not work with sense lines narrower than about 1 micron. This was due to magnetization curling from the edges of the stripe, where the magnetization is pinned along the stripe. Due to exchange, there are limits to how quickly the magnetization can change directions with distance, and near the center of a 1 micron stripe, the magnetizations of the two magnetic layers in the sandwich would be directed substantially along the stripe, thus storing data very marginally.


   MRAM  technology  has  characteristics  which  make  it  attractive   when  compared with competing technologies.There are a number of solid state, nonvolatile, read/write memories which are already in production—including two hybrid memories which combine a volatile memory with a battery, for backup power, or a true nonvolatile memory for power down backup. Only the hybrid memories can match  the  speed   of  MRAM, but

because they are not monolithic integrated devices, they will not be cost competitive, in equivalent volumes, with MRAM. Other nonvolatile memories are both slower than MRAM and have limited cycling endurance. Specific characteristics of these nonvolatile memories are given in the following paragraphs.

• EEPROM—The electrically erasable programmable read only memory boasts fast, unlimited readout. However, the write cycle is very slow (10 msec), requires high voltages, and can  only  be  done 10 5  times  before
the memory fails. While voltage boost circuitry can be included on the memory die so the EEPROM can operate from a single supply; this circuitry takes up die area, leading to higher cost. MRAM offers unlimited write cycles, high speed for both read and write, and single supply operation without additional power supply .
• Flash—Like EEPROM, most flash memories require high voltage for writing and has low cycling endurance, 10 6 cycles. At 5 to 10 msec, the write speed is considerable faster than EEPROM, but still almost three
orders of magnitude slower than DRAM and SRAM.

• FRAM—In terms of write speed and cycling endurance, ferroelectric RAM offers considerable improvement over EEPROM and flash. FRAM has a cycling endurance of up to 10 12 and writes as quickly as 150 nsec. In addition, voltage pumps are not required down to 2.7 V supplies. On the

down side, FRAM has a destructive readout, so a write cycle is required with every read, data retention time degrades significantly at moderate temperatures, 70° to 85°C, and the cycling endurance is still grossly inadequate for the high speed capability. With a cycle endurance of only 10 12 , the memory will wear out after only 42 hours when cycled continuously at 150 nsec.
• Nonvolatile RAM—This type of nonvolatile memory combines both a volatile and nonvolatile memory together into a single memory. Using SRAM for normal storage and EEPROM or flash for SRAM backup on
Resistance .
    Unlimited cycling endurance and high speed read and write are key advantages of MRAM over most other nonvolatile technologies described earlier. Additionally, a low power requirement for writing combined with the intrinsically high speed write capability of the magnetic storage   element

yields a very low energy requirement for MRAM operation. Also, MRAM is intrinsically radiation immune and can also be used in high temperature applications. These attributes allow MRAM to fill all memory applications, both nonvolatile and high speed main memory, as well as fitting well with low power and/or battery powered applications, for which the low energy characteristic is particularly important.

  MRAM has potential in all memory applications. These applications can be broken into two broad categories: dense memories and specialized memories. In addition to the application of MRAM as a replacement for EEPROM and flash memories, especially for applications where radiation hardness is required, MRAM can also be utilized as a gap memory when used with flash or EEPROM. One example is a buffer memory for flash memory systems. Flash is very limited in write speed, and because of the limited write life, must use replacement algorithms for frequently addressed words. By using an MRAM buffer, the write speed could be greatly improved, especially in burst modes, and the most frequently used addresses could be replaced with MRAM word addresses, thus extending the life of the memory system for a given application. Finally, the storing of use data for word addresses could be done in MRAM, once again extending the life of the system. Clearly, flash memory is useful today without MRAM, but there is potential for much broader use if an MRAM buffer were used in conjunction with flash.


  Several other large companies  currently   have  R&D  programs on  MRAM Technology. Honeywell has announced working MRAM components.  
 With numerous competitors in the field, there has been a reluctance to publish results. But it is clear that MRAM has the potential to be as fast and dense as DRAM with the additional advantage of nonvolatility. Compared with flash and EEPROMs, MRAM writes much faster and does not deteriorate with millions of write cycles.
 Motorola Inc. today said it has successfully demonstrated a Magnetoresistive Random Access Memory (MRAM) architecture that it claims will eventually replace commodity memory like DRAM and flash in wireless devices.
  Motorola Labs, in conjunction with the DigitalDNA Laboratories of the company's Semiconductor Products Sector, said the 3-V nonvolatile memory offers address access times of less than 15ns and a nearly unlimited  endurance of several billion read and write cycles.
  The company will now work to increase densities to meet commodity market requirements and said it expects products using the technology to be available in the next few years.

  The architecture, which was presented in February at the IEEE International Solid State Circuits Conference in San Francisco, is based on a single transistor and magnetic tunnel junction (MTJ) structure where the MTJ is integrated on top of the transistor to achieve a small cell size. While offering dramatically lower costs, MRAM is also able to wring even greater

performance out of the device by shrinking linewidths, according to Motorola.
  In April, at the IEEE International Magnetic Conference, Motorola said its MRAM chips achieved a 14ns address access time and cycle time of 24ns using a 0.6-micron process geometry. By manufacturing the design on leading-edge processes, Motorola said it will deliver speeds fast enough to displace DRAM, flash-memory chips, and all but the fastest SRAM devices.
  MRAM has also been an ambitious IBM Research Project , combining the high density of DRAM and the high density of SRAM.

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