VHSIC Hardware Description Language - VHDL

VHDL (VHSIC Hardware Description Language) is a language for describing hardware. Its requirement emerged during the VHSIC development program of the US Department of Defense. The department organized a work shop in 1981 to lay down the specifications of a language which could describe hardware at various levels of abstractions, could generate test signals and record responses, and could act as a medium of information exchange between the chip foundries and the CAD tool operators. However, due to military restrictions, it remained classified till 1985.

There was a large participation of the private sector electronics industry in the development of the language. It felt that there was a need to make the language industry standard. In 1985, the DOD granted a permission to hand over the specs to IEEE. Subsequently IEEE released the

IEEE 1076/A standard in 1987. It was later revised in 1993. The 1993 revisions are minor and many of the simulation and synthesis tools have not yet adopted them. It is an object-oriented language and therefore people familiar with C++ or PASCAL can grasp it easily.

VHDL can wear many hats. It is being used for documentation, verification, and synthesis of large digital designs. This is actually one of the key features of VHDL, since the same VHDL code can theoretically achieve all three of these goals, thus saving a lot of effort. In addition to being used for each of these purposes, VHDL can be used to take three different approaches to describing hardware. These three different approaches are the structural, data flow, and behavioral methods of hardware description. Most of the time a mixture of the three methods is employed. The following sections introduce you to the language by examining its use for each of these three methodologies

Structural Descriptions

          We will discuss the first of the three approaches to design with VHDL, the structural description.

 Building Blocks

          To make designs more understandable and maintainable, a design is typically decomposed into several blocks. These blocks are then connected together to form a complete design. Using the schematic capture approach to design, this might be done with a block diagram editor. Every portion of a VHDL design is considered a block. A VHDL design may be completely described in a single block, or it may be decomposed in several blocks. Each block in VHDL is analogous to an off-the-shelf part and is called an entity. The entity describes the interface to that block and a separate part associated with the entity describes how that block operates. The interface description is like a pin description in a data book, specifying the inputs and outputs to the block. The description of the operation of the part is like a schematic for the block.

The following is an example of an entity declaration in VHDL.

entity latch is

  port (s,r: in bit;

        q,nq: out bit);

end latch;

          The first line indicates a definition of a new entity, whose name is latch. The last line marks the end of the definition. The lines in between, called the port clause, describe the interface to the design. The port clause contains a list of interface declarations. Each interface declaration defines one or more signals that are inputs or outputs to the design.

          Each interface declaration contains a list of names, a mode, and a type. In the first interface declaration of the example, two input signals are defined, s and r. The list to the left of the colon contains the names of the signals, and to the right of the colon is the mode and type of the signals. The mode specifies whether this is an input (in), output (out), or both (inout). The type specifies what kind of values the signal can have. The signals s and r are of mode in (inputs) and type bit. Next the signals q and nq are defined to be of the mode out (outputs) and of the type bit (binary).

          All of the signals in the example are defined to be of the type bit. The type bit is a predefined type that can have two values represented by '0' and '1'. This type is used to represent two level logic signals.

          The second part of the description of the latch design is a description of how the design operates. This is defined by the architecture declaration. The following is an example of an architecture declaration for the latch entity.

architecture dataflow of latch is

  signal q0: bit: = '0';

  signal nq0: bit: = '1';

begin

  q0<=r nor nq0;

  nq0<=s nor q0;

  nq<=nq0;

  q<=q0;

end dataflow;

          The first line of the declaration indicates that this is the definition of a new architecture called dataflow and it belongs to the entity named latch. So this architecture describes the operation of the latch entity. The lines in between the begin and end describe the latch's operation. This example uses the data flow approach which is discussed later, so we won't discuss the meaning of these lines here. The next section explains how to specify the latch's operation using the structural approach.

Connecting Blocks

            Once we have defined the basic building blocks of our design using entities and their associated architectures, we can combine them together to form other designs. This section describes how to combine these blocks together in a structural description.

          Let's specify the operation of the latch entity used in the previous section by connecting some previously defined entities. The entity declaration for the latch was:

The lines between the first and the keyword begin are a component declaration. It describes the interface of the entity nor_gate that we would like to use as a component in (or part of) this design. Between the begin and end keywords, the first two lines and second two lines define two component instances.

          There is an important distinction between an entity, a component, and a component instance in VHDL. The entity describes a design interface, the component describes the interface of an entity that will be used as an instance (or a sub-block), and the component instance is a distinct copy of the component that has been connected to other parts and signals. The entity and architecture is like the data book describing the interface and schematics of how the part works. The component is like the short pin listing that comes with the part to describe how it should be connected. The component instance is the actual part itself, of which you may have many that each operate independently.

          In this example the component nor_gate has two inputs (a and b) and an output (c). There are two instances of the nor_gate component in this architecture corresponding to the two nor symbols in the schematic. The first instance represents the top nor gate in the schematic. The first line of the component instantiation statement gives this instance a name, n1, and specifies that it is an instance of the component nor_gate. The second line describes how the component is connected to the reset of the design using the port map clause.

          The port map clause specifies what signals of the design to connect to the interface of the component in the same order as they are listed in the component declaration. The second instance, named n2, connects s to a, q to b, and nq to c of a different instance of the same nor_gate component in the same manner as shown in the schematic.

          The structural description of a design is simply a textual description of a schematic. A list of components and there connections in any language is sometimes called a netlist.

Data Flow Descriptions

The data flow description is the second of the three paradigms for describing hardware with VHDL.

A First Example

         

          In the data flow approach, circuits are described by indicating how the inputs and outputs of built-in primitive components (ex. an and gate) are connected together. In other words we describe how signals (data) flow through the circuit. Let's look at the first example.

 How it Works ?

In the last section we saw an example of a data flow description and what it describes. In this section we will learn how a simulator uses that description to model the design.

The VHDL standard not only describes how designs are specified, but also how they should be interpreted. This is the purpose of having standards, so that we can all agree on the meaning of a design. It is important to understand how a VHDL simulator interprets a design because that dictates what the "correct" interpretation is according to the standard (Hopefully, simulators are not all 100% correct).

          The scheme used to model a VHDL design is called discrete event time simulation. When the value of a signal changes, we say an event has occurred on that signal. If data flows from signal A to signal B, and an event has occurred on signal A (i.e. A's value changes), then we need to determine the possibly new value of B. This is the foundation of the discrete event time simulation. The values of signals are only updated when certain events occur and events occur at discrete instances of time.

          Since one event causes another, simulation proceeds in rounds. The simulator maintains a list of events that need to be processed. In each round, all events in a list are processed, any new events that are produced are placed in a separate list (and are said to be scheduled) for processing in a later round. Each signal assignment is evaluated once, when simulation begins to determine the initial value of each signal.

Let us examine how the event time simulation proceeds for the previous example of an SR latch. The following is a schematic version of the SR latch.

CONCLUSION

          The VHDL Language can be regarded as an integrated amalgamation of the    following languages:

          Sequential language +     

          Concurrent languages+

          Net-listing language+

          Timing specifications+ 

        Waveform generation language = VHDL