16 BIT RISC Microcontroller - Engineering Seminar

The concept of the project is to design an IP (Intellectual Property) core, of a 16 bit microcontroller. The hardware description language (HDL) to be used is VHDL. VLSI tools available are Modelsim for simulation and Xilinx ISE for synthesis. The scope of project extends up to synthesis and direct implementation on an FPGA. The microcontroller executes the program stored in the on chip program memory and the output is viewed by LEDs /and 7 segment displays.

The features of the core are:
  • 16 bit CPU
  • 16 bit ALU
  • 16 bit General Purpose Registers
  • 128 bytes of on-chip Program Memory
  • 16 addressable I/O lines
  • 16 addressable I/O lines


A microcontroller is a computer-on-a-chip, or, if you prefer, a single-chip computer. Micro suggests that the device is small, and controller tells you that the device might be used to control objects, processes, or events. Another term to describe a microcontroller is embedded controller, because the microcontroller and its support circuits are often built into, or embedded in, the devices they control. You can find microcontrollers in all kinds of things these days. Any device that measures, stores, controls, calculates, or displays information is a candidate for putting a microcontroller inside. The largest single use for microcontrollers is in automobiles—just about every car manufactured today includes at least one microcontroller for engine control, and often more to control additional systems in the car. In desktop computers, you can find microcontrollers inside keyboards, modems, printers, and other peripherals. In test equipment, microcontrollers make it easy to add features such as the ability to store measurements, to create and store user routines, and to display messages and waveforms. Consumer products that use microcontrollers include cameras, video recorders, compact-disk players, and ovens. And these are just a few examples.
A microcontroller is similar to the microprocessor inside a personal computer. Examples of microprocessors include Intel’s 8086, Motorola’s 68000, and Zilog’s Z80. Both microcontrollers  and microprocessors’ contain a central processing unit, or CPU. The CPU executes instructions that perform the basic logic, math, and data-moving functions of a computer. To make a complete computer, a microprocessor requires memory for storing data and programs, and input/output (I/O) interfaces for connecting external devices like keyboards and displays. In contrast, a microcontroller is a single-chip computer because it contains memory and I/O interfaces in addition to the CPU. Because the amount of memory and interfaces that can fit on a single chip is limited, microcontrollers tend to be used in smaller systems that require little more than the microcontroller and a few support components. Examples of popular Microcontrollers are Intel’s 8052 (including the 8052-BASIC, which is the focus of this book), Motorola’s 68HC11, and Zilog’s Z8.

Micro controller includes CPU, RAM, ROM, serial and parallel interface timer, interrupt scheduling circuitry. The important feature is it has built in interrupt system. Micro controllers are often called upon to respond to external stimuli (interrupts) in real time. Microcontrollers are specialized.  They are not used in computer per se; but in industrial and consumer products. They have increased ROM to RAM ratio.

Timer can interrupt a time sharing operating system at specified intervals so that it can switch programs. It can send timing signals at periodic intervals to I/O devices. For eg the start of conversion signal to ADC .
It can be used as baud rate generator, for e.g the timer can be used as a clock divider to divide the processor clock to desired frequency for T*C and R*C of USART. It can be used to measure the time between external events. It can be used as an external event counter to count repetitive external operations and inform the count value to the processor. The timer can be used to initiate an activity through interrupt after a programmed number of external events have occurred.
The timing diagrams are shown below.
Our attempt is to design an IP core, of a 16 bit microcontroller which can easily perform the functions of  a micro controller. The hardware description language (HDL) to be used is VHDL. VLSI tools available are Modelsim for simulation and Xilinx ISE for synthesis .The microcontroller executes the program stored in the on chip program memory  The output is viewed by LEDs / 7 segment displays.
The basic parts of a 16 bit RISC microcontroller consists of 4 main blocks, they are ALU, registers, program memory, instruction decoder.

Apart from some special situations like a halt instructions or the reset, the CPU constantly executes program instructions. It is the task of the controlling unit to determine which operation should be executed next and to configure the data path accordingly. To do so, another special register, the program counter (pc), is used to store the address of the next program instruction, the control unit loads this instruction into the instruction register (IR) decodes the instruction and sets up the data path to execute it.
Data path configuration includes providing the appropriate inputs for the ALU (from register or memory) selecting the right ALU operation and making sure that the result is written to the correct destination (register or memory). The pc is either incremented to point to the next instruction in the sequence, or is loaded with a new address in the case of a jump or subroutine call. after a reset, the pc is typically initialized to$0000.Traditionally the control unit was hardwired that is it basically contained a look up table which helps the values of the control lines necessary to perform the instruction plus a rather complex decoding logic, this men that it was difficult to change or extend the instruction set of the CPU.
To ease the design of the control unit Maurice Wilkes reflected that the control unit is actually a small CPU by itself and could benefit from its own set of micro instructions. In this subsequent control unit design, program instructions were broken down into micro instructions, each of which did some small part of the whole instruction.(like providing the correct register for the ALU. This essentially made control design a programming task.
 Adding a new instruction to the instruction set boiled down to programming the instruction in microcode. As a consequence, it suddenly became comparatively easy to add new and complex instructions, and the instruction set grew rather larger and powerful as a result. This earned the architecture the name Complex Instruction Set Computer (CISC). Of course, the powerful instruction set has its price and this price is speed microcoder instructions executes slower than hardwired ones. Furthermore, studies revealed that only 20% of the instructions of a CISC machine are responsible for 80% of the code (80/20 rule).This and the fact that these complex instructions can be implemented by a combination of simple ones gave rise to a movement back towards simple hardwired architectures, which were correspondingly called Reduced Instruction Set Computer (RISC)

It contains the working registers of the CPU.It may either consist of a set of general purpose registers (generally 16-32, but there can also be more), each of which can be the source or destination of an operation, or it consist of some dedicated registers. These registers are example an accumulator which is used for arithmetic or logical operations, or an index register, which is used for some addressing modes.
  In any case the CPU can take the operands for the ALU from the file, and it can store the operations result back to the register file. Alternatively, operands/result can come from /be stored to the memory. However memory access is much slower than access to the register file, so it is usually wise to use register file if possible.

The stack is a portion of consecutive memory in the data space which is used by the CPU to store written addresses and possibly register contents during subroutine and interrupt service routine calls. It is accessed with the commands PUSH (put something on the stack) and POP (removes something from the stack). To store the current fill level of the stack, the CPU contains a special register called the stack pointer (sp), which points to the top of stack. stacks typically grow “ down “, that is , from the higher memory addresses to the lower addresses. So the sp generally starts at the end of data memory and is decremented with every push and incremented with every pop. The reason for placing the stack pointer at the end of the data memory is that your variables are generally at the start of the data memory, so by putting the stack at the end of the memory it takes longest for the two to collide. Unfortunately there are two ways to interpret the memory locations to which the sp points: it can either be seen as the first free address, so a push should stop data there and then decrement the stack pointer he Atmel AVR controllers use the sp that way, or it can be seen as the last used address, so a push first decrements the sp and then stores the data at the new address (this interpretation is adopted for e.g. in Motorola, HCS 12). Since the sp must be initialized by the programmer, you must look up how your controller handles the stack operation (write first) to the last addressing memory (if a push stores first and decrements afterwards) or to the last address + 1(if the push decrements first) as we have mentioned, the controller uses the stack during subroutine calls and interrupts,  ie  whenever the program is flow and should resume later on. Since the return address is a pre requisite for resuming program execution after the point of interruption, every controller pushes at least the written address on to the stack. Some controllers even save register on the stack to ensure that they do not get overwritten by the interrupting code. This is mainly done by controllers which only have a small set of dedicated registers.

At the core of the CPU is the arithmetic logic unit, which is used to perform computations (and, add, Inc).several control lines select which operation the ALU should perform on the input data. The ALU tales two inputs and returns the result of the operation as its output. Source and destination are taken from registers or memory. In addition the ALU stores some information about the nature of the result in the status register (also called condition code register).z (0):.the result of the operation is zero .o (overflow).the operation produced an overflow i.e. there was a change of sign in a twos compliment operation (carry).  The operation produced a carry.

The register file is just a small memory embedded in the CPU also we briefly mentioned data being transferred between registers and the data memory, and instructions been fetched from the instruction memory.
Register file
A relatively small memory embedded on the CPU. It is used as a scratch pad for temporary storage of values the CPU is working with- you should call it the CPU’s short term memory.
Data memory
For longer term storage, generic CPU’s usually employing an external memory which is much larger than the register file. Data that is stored there may be short lived, but may also be valid for as long as the CPU’s running .Of course attaching external file to a CPU require some hard ware effort and thus incurred some cost. For that reason micro controller usually spot on chip data memory.
Instruction memory
Like the data memory, the instruction memory is usually a relatively large external memory at least with general CPU’s. Actually with Von Neumann architecture it may even be the same physical memory as the data memory. With the microcontrollers, the instruction memory too is usually integrated right into the MCU.

Mr. George Boone inventor of micro controller has a number of interesting insights.  For instance, he states that he invented microcontroller while at Texas Instruments because of boredom.  He was working in a group designing custom Integrated Circuits. He noticed that the basic requirements for all projects were similar and this led to the idea that a general chip that was programmable could solve multiple customers’ requirements.  He also discusses the resistance in the community to this innovation.
After inventing the microcontroller, he moved to a start-up company, Litronix, that made handheld calculators.  The company was not aggressive about filing patents.  An overseas competitor was able to drive Litronix out of the market because of the differential tax rates between the U.S. and Hong Kong, U.S. regulatory rules on consumer warranties and their weak patent portfolio. 
Because Mr. Boone was the inventor of the microcontroller, he ended being involved in numerous patent lawsuits.  This has caused him to have a unique perspective on the patent system.  One of the most interesting points he makes is that design teams often fail to review the patent literature before starting the design process.  Because of this, they often reinvent designs and reviewing patent literature results in better designs.

Project Background
Wan Mohd Khalid did a similar project titled “FPGA Implementation of a RISC microcontroller”. The design is also based on Atmel AVR AT90S1200 microcontroller. The project is designed using both VHDL and schematics. Only 50% of the instructions are designed using VHDL behavioral approach, which results in large area and slow performance. Parallel ports, timer, external interrupt and other peripheral features are not included. The project size is so large that it requires 3 pieces of Altera EPF10K20.

Reduce Instruction Set Computer (RISC)
In the early 1980s, a number of computer designers were questioning the need for complex instruction sets used in the computer of the time. In studies of popular computer systems, almost 80% of the instructions are rarely being used. So they recommended that computers should have fewer instructions and with simple constructs. This type of computer is classified as reduced instruction set computer or RISC. Theterm CISC is introduced later to differentiate computers designed using the ‘old’ philosophy.
According to Daniel Tabak (1990), the first characteristic of RISC is the uniform series of single cycle, fetch-and-execute operations for each instruction implemented on the computer system being developed. A single-cycle fetch can be achieved by keeping all the instructions a standard size. The standard instruction size should be equal to the number of data lines in the system bus, connecting the memory (where the program is stored) to the CPU. At any fetch cycle, a complete single instruction will be transferred to the CPU. For instance, if the basic word size is 32 bits, and the data port of the system bus (the data bus) has 32 lines, the standard instruction length should be 32-bits. Achieving uniform (same time) execution of all instructions is much more difficult than achieving a uniform fetch. Some instructions may involve simple logical operations on a CPU register (such as clearing a register) and can be executed in a single CPU clock cycle without any problem. Other instructions may involve memory access (load from or store to memory, fetch data) or multicycle operations (multiply, divide, floating point), and may be impossible to be executed in a single cycle. Ideally, we would like to see a streamlined and uniform handling of all instructions, where the fetch and the execute stages take up the same time for any instruction, desirably, a single cycle. This is basically one of the first and most important principles inherent in the RISC design approach. All instructions go from the memory to the CPU, where they get executed, in a constant stream. Each instruction is executed at the same pace and no instruction is made to wait. The CPU is kept busy all the time. Thus, some of the necessary conditions to achieve such a streamlined operation are: Standard, fixed size of the instruction, equal to the computer word length and to the width of the data bus. Standard execution time of all instructions, desirably within a single CPU cycle. While it might not practical to hope that all instructions will execute in a single cycle, one can hope that at least 75% should. Which instructions should be selected to be on the reduced instruction list? The obvious answer is: the ones used most often. It has been established in a number of earlier studies that a relatively small percentage of instructions (10 – 20%) take up about 80% – 90% of execution time in an extended selection of benchmark programs. Among the most often executed instructions were data moves, arithmetic and logic operations. As mentioned earlier, one of the reasons preventing an instruction from being able to execute in a single cycle is the possible need to access memory to fetch operands and/or store results. The conclusion is therefore obvious – we should minimize as much as possible the number instructions that access memory during the execution stage. This consideration brought forward the following RISC principles: Memory access, during the execution stage, is done by load/store instructions only.
All operations, except load/store, are register-to-register, within the CPU. Most of the CISC systems are micro programmed, because of the flexibility that microprogramming offers the designer. Different instructions usually have micro routines of different lengths. This means that each instruction will take a number of different cycles to execute. This contradicts the principle of a uniform, streamlined handling of all instructions. An exception to this rule can be made when each instruction has a one-tone correspondence with a single microinstruction. That is, each micro routine consists of a single control word, and still let the designer benefit from the advantages of microprogramming. However, contemporary CAD tools allow the designer of hardwired control units almost as easy as micro programmed ones. This enables the single cycle rule to be enforced, while reducing transistor count. In order to facilitate the implementation of most instruction as register-to register operations, a sufficient amount of CPU general purpose registers has to be provided. A sufficiently large register set will permit temporary storage of intermediate results, needed as operands in subsequent operations, in the CPU register file. This, in turn, will reduce the number of memory accesses by reducing the number of load/store operations in the program, speeding up its run time. A minimal number of 32 general purpose CPU registers has been adopted, by most of the industrial RISC system designers.
 The characteristics of RISC architecture are summarized as follow:
·         Single-cycle instruction execution.
·         Fixed-length, easily decoded instruction format.
·         Relatively few instructions.
·         Memory access limited to load and store instructions.
·         All operations done within the registers of the CPU.
·         Hardwired rather than micro programmed control unit.
·         Relatively large (at least 32) general purpose register file.

32 bit RISC microcontroller by ieee
While power consumption has become an important design constraint very few reports of power analysis of processors are available in the literature. The processor considered is an experimental integration of a 16-bit DSP and a 32-bit RISC microcontroller, ERDI. Simulation based power analysis on a back annotated design is used to obtain data for a set of DSP application kernels and synthetic benchmarks.

 The RISC architecture has single, hardwired instructions which often take only one or a few clock cycles to execute. RISC machines feature a small and fixed code size with comparatively few instructions and few addressing modes. As a result, execution of instruction is very fast, but the instruction set is rather simple.
  Study of Hardware Description Language (VHDL) and the tools (Modelsim, Xilinx ISE)
   Design of the Instruction set for the Microcontroller (on paper).
   Dividing the Module into sub modules.
  Behavioral coding and simulation of the sub modules.
  Integration of the Top module (Microcontroller) and simulation of Instruction set using a sample program loaded on an on chip ROM.
   Synthesis of the Microcontroller using Xilinx ISE tool for Sparten 3 FPGA.
  Post Synthesis Simulation for logic and timing.
  Generating configuration (bit) files and downloading to FPGA chip on a Digilent Spartan-3 System Board.
  Testing the execution of the program on the FPGA. For testing purpose   the program outputs some data to a parallel port. The output data is displayed on 7 segment displays and LEDs.

The Spartan-3 Starter board provides a powerful, self-contained development platform for designs targeting the  Spartan-3 FPGA

highly flexible
fully user programmable
 reprogrammable logic device
advanced CMOS manufacturing technology.

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