ABSTRACT
Chameleon chips are chips whose circuitry can be tailored specifically for the problem at hand. Chameleon chips would be an extension of what can already be done with field-programmable gate arrays (FPGAS). An FPGA is covered with a grid of wires. At each crossover, there's a switch that can be semipermanently opened or closed by sending it a special signal. Usually the chip must first be inserted in a little box that sends the programming signals. But now, labs in Europe , Japan U.S.
The chips still won't change colors. But they may well color the way we use computers in years to come. It is a fusion between custom integrated circuits and programmable logic.in the case when we are doing highly performance oriented tasks custom chips that do one or two things spectacularly rather than lot of things averagely is used. Now using field programmed chips we have chips that can be rewired in an instant. Thus the benefits of customization can be brought to the mass market.
INTRODUCTION
Suppose, instead, that the
chip's circuits could be tailored specifically for the problem at hand--say,
computer-aided design--and then rewired, on the fly, when you loaded a
tax-preparation program. One set of chips, little bigger than a credit card,
could do almost anything, even changing into a wireless phone. The market for
such versatile marvels would be huge, and would translate into lower costs for
users.
So computer scientists are hatching a novel
concept that could increase number-crunching power--and trim costs as well. Call it the chameleon chip.
Chameleon chips would be an
extension of what can already be done with field-programmable gate arrays
(FPGAS).
An FPGA is covered with a grid of wires. At
each crossover, there's a switch that can be semipermanently opened or closed
by sending it a special signal. Usually the chip must first be inserted in a
little box that sends the programming signals. But now, labs in Europe , Japan U.S.
Chameleon chips
Highly flexible processors that can be reconfigured remotely in the
field, Chameleon's chips are designed to simplify communication system design
while delivering increased price/performance numbers. The chameleon chip is a high
bandwidth reconfigurable communications
processor (RCP).it aims at changing a
system's design from a remote location.
This will mean more versatile handhelds. Processors operate at 24,000 16-bit
million operations per second (MOPS), 3,000 16-bit million multiply-accumulates
per second (MMACS), and provide 50 channels of CDMA2000 chip-rate processing.
The 0.25-micron chip, the CS2112 is an
example.
These
new chips are able to rewire themselves on the fly to create the exact hardware
needed to run a piece of software at the utmost speed. an example of such kind
of a chip is a chameleon chip.this can also be called a “chip
on demand” “Reconfigurable computing goes a step beyond programmable
chips in the matter of flexibility. It is not only possible but relatively
commonplace to "rewrite" the silicon so that it can perform new
functions in a split second. Reconfigurable chips are simply the extreme end of
programmability.”
The overall performance of the
ACM can surpass the DSP because the ACM only constructs the actual hardware
needed to execute the software, whereas DSPs and microprocessors force the
software to fit its given architecture.
One reason that this type of
versatility is not possible today is that handheld gadgets are typically built
around highly optimized specialty chips that do one thing really well. These
chips are fast and relatively cheap, but their circuits are literally written
in stone -- or at least in silicon. A multipurpose gadget would have to have
many specialized chips -- a costly and clumsy solution. Alternately, you could
use a general-purpose microprocessor, like the one in your PC, but that would
be slow as well as expensive. For these reasons, chip designers are turning
increasingly to reconfigurable hardware—integrated circuits where the
architecture of the internal logic elements can be arranged and rearranged on
the fly to fit particular applications.
Designers of multimedia systems
face three significant challenges in today's ultra-competitive marketplace: Our
products must do more, cost less, and be brought to the market quicker than
ever. Though each of these goals is individually attainable, the hat trick is
generally unachievable with traditional design and implementation techniques.
Fortunately, some new techniques are emerging from the study of reconfigurable
computing that make it possible to design systems that satisfy all three requirements
simultaneously.
Although
originally proposed in the late 1960s by a researcher at UCLA, reconfigurable
computing is a relatively new field of study. The decades-long delay had mostly
to do with a lack of acceptable reconfigurable hardware. Reprogrammable logic
chips like field programmable gate arrays (FPGAs) have been around for many
years, but these chips have only recently reached gate densities making them
suitable for high-end applications. (The densest of the current FPGAs have
approximately 100,000 reprogrammable logic gates.) With an anticipated doubling
of gate densities every 18 months, the situation will only become more
favorable from this point forward.
The primary
product is a groundstation equipment for satellite communications. This
application involves high-rate communications, signal processing, and a variety
of network protocols and data formats.
FPGA
One of the most promising approaches in the
realm of reconfigurable architecture is a technology called
"field-programmable gate arrays." The strategy is to build uniform
arrays of thousands of logic elements, each of which can take on the
personality of different, fundamental components of digital circuitry; the
switches and wires can be reprogrammed to operate in any desired pattern,
effectively rewiring a chip's circuitry on demand. A designer can download a
new wiring pattern and store it in the chip's memory, where it can be easily
accessed when needed.
Not so hard after all Reconfigurable
hardware first became practical with the introduction a few years ago of a
device called a “field-programmable gate array” (FPGA) by Xilinx, an
electronics company that is now based in San
Jose , California
Evolving FPGAs
FPGAs are arrays of logic blocks
that are strung together through software commands to implement higher-order logic
functions. Logic blocks are similar to switches with multiple inputs and a
single output, and are used in digital circuits to perform binary operations.
Unlike with other integrated circuits, developers can alter both the logic
functions performed within the blocks and the connections between the blocks of
FPGAs by sending signals that have been programmed in software to the chip.
FPGA blocks can perform the same high-speed hardware functions as
fixed-function ASICs, and—to distinguish them from ASICs—they can be rewired
and reprogrammed at any time from a remote location through software. Although
it took several seconds
or more to change connections in the earliest FPGAs, FPGAs today can be configured in milliseconds.
or more to change connections in the earliest FPGAs, FPGAs today can be configured in milliseconds.
Field-programmable gate arrays
have historically been applied as what is called glue logic in embedded
systems, connecting devices with dissimilar bus architectures. They have often
been used to link digital signal processors—cpus used for digital signal
processing—to general-purpose cpus.
The growth in FPGA technology
has lifted the arrays beyond the simple role of providing glue logic. With
their current capabilities, they clearly now can be classed as system-level
components just like cpus and DSPs. The largest of the FPGA devices made by the
company with which one of the authors of this article is affiliated, for
example, has more than 150 billion transistors, seven times more than a
Pentium-class microprocessor. Given today's time-to-market pressures, it is
increasingly critical that all system-level components be easy to integrate,
especially since the phase involving the integration of multiple technologies
has become the most time-consuming part of a product's development cycle.
To Integrating Hardware and
Software systems designers producing mixed cpu and FPGA designs can take
advantage of deterministic real-time operating systems (RTOSs). Deterministic
software is suited for controlling hardware. As such, it can be used to
efficiently manage the content of system data and the flow of such data from a
cpu to an FPGA. FPGA developers can work with RTOS suppliers to facilitate the
design and deployment of systems using combinations of the two technologies.
FPGAs operating in conjunction with embedded design tools provide an ideal
platform for developing high-performance reconfigurable computing solutions for
medical instrument
applications. The platform supports the design, development, and testing of embedded systems based on the C language.
applications. The platform supports the design, development, and testing of embedded systems based on the C language.
Integration
of FPGA technology into systems using a deterministic RTOS can be streamlined
by means of an enhanced application programming interface (API). The blending of hardware, firmware,
application software, and an RTOS into a platform-based approach removes many
of the development barriers that still limit the functionality of embedded
applications. Development, profiling, and analysis tools are available that can
be used to analyze computational hot spots in code and to perform low-level
timing analysis in multitasking environments.
One way developers can use these
analytical tools is to determine when to design a function in hardware or
software. Profiling enables them to quickly identify functionality that is
frequently used or computationally intensive. Such functions may be prime
candidates for moving from software to FPGA hardware. An integrated suite of
run-time analysis tools with a run-time error checker and visual interactive
profiler can help developers create higher-quality, higher-performance code in
little time.
An FPGA consists of an array of
configurable logic blocks that implement the logical functions. In FPGA's, the
logic functions performed within the logic blocks, and sending signals to the
chip can alter the connections between the blocks. These blocks are similar in
structure to the gate arrays used in some ASIC's, but whereas standard gate
arrays are configured and fixed during manufacture, the configurable logic
blocks in new FPGA's can be rewired and reprogrammed repeatedly in around a
microsecond. One advantages of FPGA is
that it needs small time to market Flexibility and Upgrade advantages Cheap to
make .We can configure an FPGA using Very
High Density Language [VHDL] Handel C Java .FPGA’s are used presently in Encryption Image Processing Mobile Communications .FPGA’s can be used in 4G mobile communication
High Density Language [VHDL] Handel C Java .FPGA’s are used presently in Encryption Image Processing Mobile Communications .FPGA’s can be used in 4G mobile communication
The advantages of FPGAs are that
Field programmable gate arrays offer companies the possibility of develloping a
chip very quickly, since a chip can be configured by software. A chip can also
be reconfigured, either during execution time, or as part of an upgrade to
allow new applications, simply by loading new configuration into the chip. The
advantages can be seen in terms of cost, speed and power consumption. The added
functionality of multi-parallelism allows one FPGA to replace multiple ASIC’s.
The applications of FPGA’s are in
Ø image processing
Ø encryption
Ø mobile communication
Ø memory management and
digital signal processing
Ø telephone units
Ø mobile base stations.
Although it is very hard to
predict the direction this technology will take, it seems more than likely that
future silicon chips will be a combination of programmable logic, memory blocks
and specific function blocks, such as floating point units.
It is hard to predict at this
early stage, but it looks likely that the technology will have to change over
the coming years, and the rate of change for major players in todays
marketplace such as Intel, Microsoft and AMD will be crucial to their survival.
The
precise behaviour of each cell is determined by loading a string of numbers
into a memory underneath it. The way in which the cells are interconnected is
specified by loading another set of numbers into the chip. Change the first set
of numbers and you change what the cells do. Change the second set and you
change the way they are linked up. Since even the most complex chip is, at its
heart, nothing more than a bunch of interlinked logic circuits, an FPGA can be
programmed to do almost anything that a conventional fixed piece of logic
circuitry can do, just by loading the right numbers into its memory. And by
loading in a different set of numbers, it can be reconfigured in the twinkling
of an eye.
Basic reconfigurable circuits
already play a huge role in telecommunications. For instance, relatively simple
versions made by companies such as Xilinx and Altera are widely used for
network routers and switches, enabling circuit designs to be easily updated
electronically without replacing chips. In these early applications, however,
the speed at which the chips reconfigure themselves is not critical. To be
quick enough for personal information devices, the chips will need to
completely reconfigure themselves in a millisecond or less. "That kind of chameleon device would be
the killer app of reconfigurable computing" These experts predict that in the next couple
of years reconfigurable systems will be used in cell phones to handle things
like changes in telecommunications systems or standards as users travel between
calling regions -- or between countries.
As it is getting more expensive
and difficult to pattern, or etch, the elaborate circuitry used in
microprocessors; many experts have predicted that maintaining the current rate
of putting more circuits into ever smaller spaces will, sometime in the next 10
to 15 years, result in features on microchips no bigger than a few atoms, which
would demand a nearly impossible level of precision in fabricating circuitry
But reconfigurable chips don't need that
type of precision and we can make computers that function at the nanoscale
level.
CS2112
(a reconfigurable
processor developed by chameleon systems)
RCP architecture is designed to
be as flexible as an FPGA, and as easy to program as a digital signal processor
(DSP), with real-time, visual debugging capability. The development environment, comprising
Chameleon's C-SIDE software tool suite and CT2112SDM development kit, enables
customers to develop and debug communication and signal processing systems
running on the RCP. The RCP's development environment helps overcome a
fundamental design and debug challenge facing communication system designers.In
order to build sufficient performance, channel capacity, and flexibility into
their systems, today's designers have been forced to employ an amalgamation of
DSPs, FPGAs and ASICs, each of which requires a unique design and debug
environment.
The RCP platform was designed
from the ground up to alleviate this problem: first by significantly exceeding
the performance and channel capacity of the fastest DSPs; second by integrating
a complete SoC subsystem, including an embedded microprocessor, PCI core, DMA
function, and high-speed bus; and third by consolidating the design and debug
environment into a single platform-based design system that affords the
designer comprehensive visibility and control.
The C-SIDE software suite
includes tools used to compile C and assembly code for execution on the
CS2112's embedded microprocessor, and Verilog simulation and synthesis tools
used to create parallel datapath kernels which run on the CS2112's
reconfigurable processing fabric.
In
addition to code generation tools, the package contains source-level debugging
tools that support simulation and real-time debugging. Chameleon's design
approach leverages the methods employed by most of today's communications
system designers. The designer starts with a C program that models signal
processing functions of the baseband system. Having identified the dataflow
intensive functional blocks, the designer implements them in the RCP to
accelerate them by 10- to 100-fold.
The designer creates equivalent
functions for those blocks, called kernels, in Chameleon's reconfigurable
assembly language-like design entry language. The assembler then automatically
generates standard Verilog for these kernels that the designer can verify with
commercial Verilog simulators. Using these tools, the designer can compare
testbench results for the original C functions with similar results for the
Verilog kernels. In the next phase, the designer synthesises the Verilog
kernels using Chameleon's synthesis tools targeting Chameleon technology. At
the end, the tools output a bit file that is used to configure the RCP.The
designer then integrates the application level C code with Verilog kernels and
the rest of the standard C function.Chameleon's C-SIDE compiler and linker
technology makes this integration step transparent to the designer.
The CS2112
development environment makes all chip registers and memory locations
accessible through a development console that enables full processor-like
debugging, including features like single-stepping and setting breakpoints. Before
actually productising the system, the designer must often perform a
system-level simulation of the data flow within the context of the overall
system. Chameleon's development board enables the designer to connect multiple
RCPs to other devices in the system using the PCI bus and/or programmable I/O
pins.
This
helps prove the design concept, and enables the designer to profile the
performance of the whole basestation system in a real-world environment. With telecommunications OEMs facing shrinking
product life cycles and increasing market pressures, not to mention the
constant flux of protocols and standards, it's more necessary than ever to have
a platform that's reconfigurable. This is where the chameleon chips are going
to make its effect felt.
The
Chameleon CS2112 Package is a high-bandwidth, reconfigurable communications
processor aimed at
v second- and
third-generation wireless base stations
v fixed point wireless local
loop (WLL)
v voice over IP
v DSL(digital subscriber
line)
v High end dsp operations
v 2G-3G wireless base
stations
v software defined radio
v security processing
"Traditional solutions such
as FPGAs and DSPs lack the performance for high-bandwidth applications, and
fixed function solutions like ASICs incur unacceptable limits Each product in
the CS2000 family has the same fundamental functional blocks: a 32-bit RISC
processor, a full-featured memory controller, a PCI controller, and a
reconfigurable processing fabric, all of which are interconnected by a
high-speed system bus. The above mentioned
fabric comprises an array of reconfigurable tiles used to implement the desired
algorithms. Each tile contains seven 32-bit reconfigurable datapath units, four
blocks of local store memory, two 16x24-bit multipliers, and a control logic
unit.
Components:
v 32-bit Risc ARC processor
@125MHz
v 64 bit memory controller
v 32 bit PCI controller
v reconfigurable processing
fabric (RPF)
v high speed system bus
v programmable I/O (160
pins)
v DMA Subsystem
v Configuration Subsystem
More on the architecture
of RPF4
Slices with 3 Tiles in each. Each tile can be reconfigured at runtime Tiles contain :
·
Datapath Units
·
Local Store Memories
·
16x24 multipliers
·
Control Logic Unit
The C-SIDE design system is a
fully integrated tool suite, with C compiler, Verilog synthesizer, full-chip
simulator, as well as a debug and verification environment -- an element not
readily found in ASIC and FPGA design flows, according to Chameleon. Still,
reconfigurable chips represent an attempt to combine the best features of
hard-wired custom chips, which are fast and cheap, and programmable logic
device (PLD) chips, which are flexible and easily brought to market.
Unlike PLDs, QuickSilver's
reconfigurable chips can be reprogrammed every few nanoseconds, rewiring
circuits so they are processing global positioning satellite signals one moment
or CDMA cellular signals the next, Think
of the chips as consisting of libraries with preset hardware designs and
chalkboards. Upon receiving instructions from software, the chip takes a
hardware component from the library (which is stored as software in memory) and
puts it on the chalkboard (the chip). The chip wires itself instantly to run
the software and dispatches it. The hardware can then be erased for the next
cycle. With this style of computing, its chips can operate 80 times as fast as
a custom chip but still consume less power and board space, which translates
into lower costs. The company believes
that "soft silicon," or chips that can be reconfigured on the fly,
can be the heart of multifunction camcorders or digital television sets.
With programmable logic devices,
designers use inexpensive software tools to quickly develop, simulate, and test
their designs. Then, a design can be quickly programmed into a device, and
immediately tested in a live circuit. The PLD that is used for this prototyping
is the exact same PLD that will be used in the final production of a piece of
end equipment, such as a network router, a DSL modem, a DVD player, or an
automotive navigation system.
The two major types of
programmable logic devices are field programmable gate arrays (FPGAs) and
complex programmable logic devices (CPLDs). Of the two, FPGAs offer the highest
amount of logic density, the most features, and the highest performance FPGAs
are used in a wide variety of applications ranging from data processing and
storage, to instrumentation, telecommunications, and digital signal processing.
To overcome these limitations
and offer a flexible, cost-effective solution, many new entrants to the DSP
market are extolling the virtues of configurable and reconfigurable DSP
designs. This latest breed of DSP architectures promises greater flexibility to
quickly adapt to numerous and fast-changing standards. Plus, they claim to
achieve higher performance without adding silicon area, cost, design time, or
power consumption. In essence, because the architecture isn't rigid, the
reconfigurable DSP lets the developer tailor the hardware for a specific task,
achieving the right size and cost for the target application. Moreover, the
same platform can be reused for other applications.
Because development tools are a
critical part of this solution—in fact, they're true enablers—the newcomers
also ensure that the tools are robust and tightly linked to the devices'
flexible architectures. While providing an intuitive, integrated development
environment for the designers, the manufacturers ensure affordability as well.
RECONFIGURING
THE ARCHITECTURE
Some of the new
configurable DSP architectures are reconfigurable too—that is, developers can
modify their landscape on the fly, depending on the incoming data stream. This
capability permits dynamic reconfigurability of the architecture as demanded by
the application. Proponents of such chips are proclaiming an era of
"chip-on-demand," wherein new algorithms can be accommodated on-chip
in real time via software. This eliminates the cumbersome job of fitting the
latest algorithms and protocols into existing rigid hardware. A reconfigurable
communications processor (RCP) can reconfigured for different processing
algorithms in one clock cycle.
Chameleon designers are revising the architecture to create a
chip that can address a much broader range of applications. Plus, the supplier
is preparing a new, more user-friendly suite of tools for traditional DSP
designers. Thus, the company is dropping the term reconfigurability for the new
architecture and going with a more traditional name, the streaming data processor
(SDP).
Though the SDP will include a reconfigurable processing
fabric, it will be substantially altered, the company says. Unlike the older
RCP, the new chip won't have the ARM RISC core, and it will support a much
higher clock rate. Additionally, it will be implemented in a 0.13-µm CMOS
process to meet the signal processing needs of a much broader market. Further
details await the release of SDP sometime in the first quarter of 2003.
While
Chameleon is in the redesign mode, QuickSilver Technologies is in the test
mode. This reconfigurable proponent, which prefers to call its architecture an
adaptive computing machine or ACM, has realized its first silicon test chip. In fact, the tests indicate that it
outperforms a hardwired, fixed-function ASIC in processing compute-intensive
cdma2000 algorithms, like system acquisition, rake finger, and set maintenance.
For example, the ASIC's nominal speed for searching 215 phase offsets in a
basic multipath search algorithm is 3.4 seconds. The ACM test chip took just
one second at a 25-MHz clock speed to perform the same number of searches in a
cdma2000 handset. Likewise, the device accomplishes over 57,000 adaptations per
second in rake-finger operation to cycle through all operations in this
application every 52 µs (Fig. 1). In the set-maintenance application, the chip
is almost three times faster than an ASIC, claims QuickSilver.
THE power of a computer stems from the fact
that its behaviour can be changed with little more than a dose of new software.
A desktop PC might, for example, be browsing the Internet one minute, and
running a spreadsheet or entering the virtual world of a computer game the
next. But the ability of a microprocessor (the chip that is at the heart of any
PC) to handle such a variety of tasks is both a strength and a weakness—because
hardware dedicated to a particular job can do things so much faster.
Recognising this, the designers
of modern PCs often hand over such tasks as processing 3-D graphics, decoding
and playing movies, and processing sound—things that could, in theory, be done
by the basic microprocessor—to specialist chips. These chips are designed to do
their particular jobs extremely fast, but they are inflexible in comparison
with a microprocessor, which does its best to be a jack-of-all-trades. So the
hardware approach is faster, but using software is more flexible.
At the moment,
such reconfigurable chips are used mainly as a way of conjuring up specialist
hardware in a hurry. Rather than designing and building an entirely new chip to
carry out a particular function, a circuit designer can use an FPGA instead.
This speeds up the design process enormously, because making changes becomes as
simple as downloading a new configuration into the chip. Chameleon Systems also develops reconfigurable
chips for the high-end telecom-switching market.
RECONFIGURABLE
PROCESSORS
A reconfigurable processor is a
microprocessor with erasable hardware that can rewire itself dynamically. This
allows the chip to adapt effectively to the programming tasks demanded by the
particular software they are interfacing with at any given time. Ideally, the
reconfigurable processor can transform itself from a video chip to a central
processing unit (cpu) to a graphics chip, for example, all optimized to allow
applications to run at the highest possible speed. The new chips can be called
a "chip on demand." In
practical terms, this ability can translate to immense flexibility in terms of
device functions. For example, a single device could serve as both a camera and
a tape recorder (among numerous other possibilities): you would simply download
the desired software and the processor would reconfigure itself to optimize
performance for that function.
Reconfigurable
processors, competing in the market with
traditional hard-wired chips and several types of programmable microprocessors.
Programmable chips have been in existence for over ten years. Digital signal
processors (DSPs), for example, are high-performance programmable chips used in
cell phones, automobiles, and various types of music players.
While
microprocessors have been the dominant devices in use for general-purpose
computing for the last decade, there is still a large gap between the
computational efficiency of microprocessors and custom silicon. Reconfigurable
devices, such as FPGAs, have come closer to closing that gap, offering a 10x
benefit in computational density over microprocessors, and often offering
another potential 10x improvement in yielded functional density on low
granularity operations. On highly regular computations, reconfigurable
architectures have a clear superiority to traditional processor architectures.
On tasks with high functional diversity, microprocessors use silicon more
efficiently than reconfigurable devices. The BRASS project is developing a
coupled architecture which allow a reconfigurable array and processor core to
cooperate efficiently on computational tasks, exploiting the strengths of both
architectures.
We are developing an architecture and a prototype component
that will combine a processor and a high performance reconfigurable array on a
single chip. The reconfigurable array extends the usefulness and efficiency of
the processor by providing the means to tailor its circuits for special tasks.
The processor improves the efficiency of the reconfigurable array for
irregular, general-purpose computation.
We anticipate that a processor combined with reconfigurable
resources can achieve a significant performance improvement over either a
separate processor or a separate reconfigurable device on an interesting range
of problems drawn from embedded computing applications. As such, we hope to
demonstrate that this composite device is an ideal system element for embedded
processing.
Reconfigurable devices have proven extremely efficient for
certain types of processing tasks. The key to their cost/performance advantage
is that conventional processors are often limited by instruction bandwidth and
execution restrictions or by an insufficient number or type of functional
units. Reconfigurable logic exploits more program parallelism. By dedicating
significantly less instruction memory per active computing element,
reconfigurable devices achieve a 10x improvement in functional density over
microprocessors. At the same time this lower memory ratio allows reconfigurable
devices to deploy active capacity at a finer grained level, allowing them to
realize a higher yield of their raw capacity, sometimes as much as 10x, than
conventional processors.
The high fuctional density characteristic of reconfigurable
devices comes at the expense of the high functional diversity characteristic of
microprocessors. Microprocessors have evolved to a highly optimized
configuration with clear cost/performance advantages over reconfigurable arrays
for a large set of tasks with high functional diversity. By combining a
reconfigurable array with a processing core we hope to achieve the best of both
worlds.
While it is possible to combine a conventional processor with
commercial reconfigurable devices at the circuit board level, integration
radically changes the i/o costs and design point for both devices, resulting in
a qualitatively different system. Notably, the lower on-chip communication
costs allow efficient cooperation between the processor and array at a finer
grain than is sensible with discrete designs.
RECONFIGURABLE
COMPUTING
When we talk about reconfigurable computing we’re usually
talking about FPGA-based system designs. Unfortunately, that doesn’t qualify
the term precisely enough. System designers use FPGAs in many different ways.
The most common use of an FPGA is for prototyping the design of an ASIC. In
this scenario, the FPGA is present only on the prototype hardware and is
replaced by the corresponding ASIC in the final production system. This use of
FPGAs has nothing to do with reconfigurable computing.
However, many system designers
are choosing to leave the FPGAs as part of the production hardware. Lower FPGA prices and higher gate counts have helped drive
this change. Such systems retain the execution speed of dedicated hardware but
also have a great deal of functional flexibility. The logic within the FPGA can
be changed if or when it is necessary, which has many advantages. For example,
hardware bug fixes and upgrades can be administered as easily as their software
counterparts. In order to support a new version of a network protocol, you can
redesign the internal logic of the FPGA and send the enhancement to the
affected customers by email. Once they’ve downloaded the new logic design to
the system and restarted it, they’ll be able to use the new version of the
protocol. This is configurable computing; reconfigurable computing goes one
step further.
Reconfigurable computing
involves manipulation of the logic within the FPGA at run-time. In other words,
the design of the hardware may change in response to the demands placed upon
the system while it is running. Here, the FPGA acts as an execution engine for
a variety of different hardware functions — some executing in parallel, others
in serial — much as a CPU acts as an execution engine for a variety of software
threads. We might even go so far as to call the FPGA a reconfigurable
processing unit (RPU).
Reconfigurable computing allows
system designers to execute more hardware than they have gates to fit, which
works especially well when there are parts of the hardware that are
occasionally idle. One theoretical application is a smart cellular phone that
supports multiple communication and data protocols, though just one a time.
When the phone passes from a geographic region that is served by one protocol
into a region that is served by another, the hardware is automatically
reconfigured. This is reconfigurable computing at its best, and using this approach
it is possible to design systems that do more, cost less, and have shorter
design and implementation cycles.
Reconfigurable computing
has several advantages.
Ø First, it is possible to
achieve greater functionality with a simpler hardware design. Because not all
of the logic must be present in the FPGA at all times, the cost of supporting
additional features is reduced to the cost of the memory required to store the
logic design. Consider again the multiprotocol cellular phone. It would be
possible to support as many protocols as could be fit into the available
on-board ROM.
Ø The second advantage is
lower system cost, which does not manifest itself exactly as you might expect.
On a low-volume product, there will be some production cost savings, which
result from the elimination of the expense of ASIC design and fabrication.
However, for higher-volume products, the production cost of fixed hardware may
actually be lower. We have to think in terms of lifetime system costs to see
the savings. Systems based on reconfigurable computing are upgradable in the
field. Such changes extend the useful life of the system, thus reducing
lifetime costs.
Ø The final advantage of
reconfigurable computing is reduced time-to-market. The fact that you’re no
longer using an ASIC is a big help in this respect. There are no chip design
and prototyping cycles, which eliminates a large amount of development effort.
In addition, the logic design remains flexible right up until (and even after)
the product ships. This allows an incremental design flow, a luxury not
typically available to hardware designers. You can even ship a product that
meets the minimum requirements and add features after deployment. In the case
of a networked product like a set-top box or cellular telephone, it may even be
possible to make such enhancements
without customer involvement.
RECONFIGURABLE
HARDWARE
Traditional FPGAs are
configurable, but not run-time reconfigurable. Many of the older FPGAs expect
to read their configuration out of a serial EEPROM, one bit at a time. And they
can only be made to do so by asserting a chip reset signal. This means that the
FPGA must be reprogrammed in its entirety and that its previous internal state
cannot be captured beforehand. Though these features are compatible with
configurable computing applications, they are not sufficient for reconfigurable
computing.
In order to benefit from
run-time reconfiguration, it is necessary that the FPGAs involved have some or
all of the following features. The more of these features they have, the more
flexible can be the system design. Deciding which hardware objects to execute
and when Swapping hardware objects into and out of the reconfigurable logic Performing routing between hardware objects or
between hardware objects and the hardware object framework. Of course, having software manage the
reconfigurable hardware usually means having an embedded processor or
microcontroller on-board. (We expect several vendors to introduce single-chip
solutions that combine a CPU core and a block of reconfigurable logic by year’s
end.) The embedded software that runs there is called the run-time environment
and is analogous to the operating system that manages the execution of multiple
software threads. Like threads, hardware objects may have priorities,
deadlines, and contexts, etc. It is the job of the run-time environment to organize
this information and make decisions based upon it.
The reason we need a run-time
environment at all is that there are decisions to be made while the system is
running. And as human designers, we are not available to make these decisions.
So we impart these responsibilities to a piece of software. This allows us to
write our application software at a very high level of abstraction. To do this,
the run-time environment must first locate space within the RPU that is large
enough to execute the given hardware object. It must then perform the necessary
routing between the hardware object’s inputs and outputs and the blocks of
memory reserved for each data stream. Next, it must stop the appropriate clock,
reprogram the internal logic, and restart the RPU. Once the object starts to
execute, the run-time environment must continuously monitor the hardware
object’s status flags to determine when it is done executing. Once it is done,
the caller can be notified and given the results. The run-time environment is then
free to reclaim the reconfigurable logic gates that were taken up by that
hardware object and to wait for additional requests to arrive from the
application software.
The
principal benefits of reconfigurable computing are the ability to execute larger
hardware designs with fewer gates and to realize the flexibility of a
software-based solution while retaining the execution speed of a more
traditional, hardware-based approach. This makes doing more with less a
reality. In our own business we have seen tremendous cost savings, simply
because our systems do not become obsolete as quickly as our competitors because
reconfigurable computing enables the addition of new features in the field,
allows rapid implementation of new standards and protocols on an as-needed
basis, and protects their investment in computing hardware.
Whether
you do it for your customers or for yourselves, you should at least consider
using reconfigurable computing in your next design. You may find, as we have,
that the benefits far exceed the initial learning curve. And as reconfigurable
computing becomes more popular, these benefits will only increase.
Conclusion
These
new chips called chameleon chips are
able to rewire themselves on the fly to create the exact hardware needed to run
a piece of software at the utmost speed.an example of such kind of a chip is a
chameleon chip.this can also be called a
“chip on demand”
Reconfigurable computing
goes a step beyond programmable chips in the matter of flexibility. It is not
only possible but relatively commonplace to "rewrite" the silicon so
that it can perform new functions in a split second. Reconfigurable chips are
simply the extreme end of programmability.”
Highly
flexible processors that can be reconfigured remotely in the field, Chameleon's
chips are designed to simplify communication system design while delivering
increased price/performance numbers.
The chameleon chip is a high bandwidth reconfigurable communications processor
(RCP).it aims at changing a system's
design from a remote location.this will
mean more versatile handhelds.
Its applications are in, data-intensive Internet,DSP,wireless
basestations, voice compression, software-defined radio, high-performance
embedded telecom and datacom
applications, xDSL concentrators,fixed
wireless local loop, multichannel voice compression, multiprotocol packet and
cell processing protocols. Its advantages
are that it can create customized
communications signal processors ,it has increased performance and channel
count, and it can more quickly adapt to
new requirements and standards and it has
lower development costs and reduce risk.
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